Hybrid module electronics package

ABSTRACT

A Very Large Hybrid Module (VLHM) for packaging electronic components provides a hermetic enclosure formed by a hermetic substrate on which the components are mounted together with a hermetic lid surrounding groups of the components. A second substrate outside the hermetic enclosure is utilized for providing connections between the electronic components.

BACKGROUND OF THE INVENTION

This invention relates to the packaging of electronic components and,more particularly, to an improved very large hybrid module having highdensity and high performance characteristics.

In recent years, there have been rapid advances in the development ofvery large scale and very high speed integrated circuits. This has ledto integrated circuit chips of ever increasing sizes, which has beenaccompanied by a dramatic increase in the required number ofinput/output leads to the chips. At the same time, the increasedfunctional density has resulted in a corresponding increase in powerdissipation requirements. While these developments are generallydesirable, problems arise because conventional single chip packagingtechniques do not offer interconnection systems compatible with highspeed operation nor do they offer a heat removal mechanism which isrequired for the high power densities achieved by these new integratedcircuit chips. At the present time, integrated circuit chips aretypically packaged in individual cases which in turn are mounted to, andinterconnected via, printed circuit boards. The increases in thefunctional capability and the input/output count of these chipscontinues to enlarge the chip package and the required packaging realestate. Typically, a two inch square is needed for a 256 input/outputpin grid array.

As the size of integrated circuit chip packages increases, the distancebetween the chips lengthens, the complexity of the printed circuit boardrises, and high speed operation deteriorates. The larger packages alsohave cumbersome thermal interfaces with high impedance thermal paths.

To overcome interconnection length problems, the semiconductor industryhas developed large multi-chip packages which employ thick or thin filminterconnect technology, thereby eliminating individual chip packages.As a means of further improving interconnections and bringing the chipsinto closer proximity, the chips are often mounted on a multi-layer fineline polyimide dielectric. Thus, packages as large as four inches squareand containing in excess of 100 chips in a single hermetic enclosurehave been developed.

Although the individual chips are tested prior to mounting on thedielectric, testing is difficult once the chips are bonded to thedielectric. Probing a field cluttered with wire bonds or TAB connectionscan lead to subtle and not readily detectable damage, possiblyinitiating a long term failure mechanism. After the lid of the hermeticenclosure is sealed, the removal of the lid, or impervious coatings, forrepair purposes and subsequent resealing pose significant problems.

A further problem with the aforedescribed arrangement is that when chipsare mounted on an organic dielectric substrate, additional thermalimpedance is introduced and there is a potential outgassing and ioniccontamination problem from the dielectric substrate within the hermeticenclosure.

An alternative to multi-chip packaging is wafer scale integrationwherein a two to four inch diameter wafer is mounted within a hermeticenclosure or under an impervious overcoat. This approach goes a long waytoward minimizing lead length, but results in poor yields, testabilityproblems and high "up front" cost.

Another recently developed packaging technique which aspires to providehermetically equivalent environmental protection by using a topicalpassivation or overcoat results in weight savings and size advantages.However, cleanliness and ionic or moisture penetration representformidable challenges.

It is therefore a primary object of this invention to provide a costeffective chip package which resolves all of the aforedescribedoutstanding problems while conforming to established industry standardsfor overall size and shape.

A more specific object of this invention is to provide an integratedcircuit chip module capable of interconnecting a multitude of high speeddevices, each having as many as several hundred input/outputconnections.

A further object of this invention is to provide such a module with anappropriate heat removal mechanism.

Yet another object of this invention is to provide such a module withdense hermetic packaging of a number of integrated circuit chips.

It is still a further object of this invention to provide such a modulewherein the interconnection system facilitates reliable chip to chipcommunication at greater than a 100 megahertz rate within a limitedarea, with localized sections being able to accommodate higher frequencycircuitry utilizing GaAs chips operating at gigahertz rates.

It is yet another object of this invention to provide such a modulewhere the interconnection medium does not introduce detrimentaloutgassing into the hermetic enclosure.

Still a further object of this invention is to provide a module whichpermits electrical signal access to every one of the chip input/outputpads from the outside of the hermetic enclosure for rapid in-circuitelectrical testing after sealing of the hermetic enclosure, with thehermetic enclosure design being able to accommodate a reasonable numberof unseal/seal cycles. Further, it is desired to have the capability ofexternal cut and jumper reworkability of the package.

SUMMARY OF THE INVENTION

The foregoing, and additional, objects are attained in accordance withthe principles of this invention by providing a module of electroniccircuitry comprising a first substrate having hermetic properties andhaving generally planar parallel first and second surfaces, a pluralityof electronic components mounted on the first surface of the firstsubstrate, the plurality of components being grouped within discreteregions of the first surface, enclosure means for providing a pluralityof hermetic enclosures on the first surface, each of the enclosuressurrounding the components within a respective discrete region, a secondsubstrate having generally planar parallel first and second surfaceswith the first surface of the second substrate being in intimate contactwith and electrically interconnected to the second surface of the firstsubstrate, and interconnection means for providing connections betweenthe plurality of electronic components through the second substrate.

In accordance with an aspect of this invention, the enclosure meansincludes a plurality of hermetic seal rings hermetically mounted on thefirst substrate first surface, each of the seal rings surrounding arespective discrete region, and a plurality of hermetic lid members eachhermetically joined to a respective one of the seal rings so as toprovide a plurality of enclosed spaces each containing the electroniccomponents within the respective discrete region.

In accordance wih another aspect of this invention, the first substrateis formed of a ceramic, which may be a co-fired ceramic, and which isselected from a group consisting of aluminum oxide and aluminum nitrideor other insulating material having similar physical properties.

In accordance with a further aspect of this invention, the secondsubstrate is formed from a polymer material.

In accordance with still a further aspect of this invention, theinterconnection means includes a plurality of conductive pads on thefirst substrate first surface, means for electrically connecting theleads of the electronic components to respective ones of the pads, afirst plurality of metallized vias through the first substrate incontact with respective ones of the pads, with the first plurality ofvias extending from the first surface to the second surface of the firstsubstrate, and a plurality of conductive signal traces through thesecond substrate interconnecting the first plurality of vias so as toprovide a desired pattern of connections between the leads of theelectronic components.

In accordance with still another aspect of this invention, the modulefurther includes a second plurality of metallized vias through thesecond substrate, the second plurality of vias being in contact withrespective ones of the first plurality of vias and extending from thefirst surface to the second surface of the second substrate.

In accordance with yet another aspect of this invention, the secondsubstrate and the plurality of conductive signal traces are togetherformed as a multi-layer conductor/polymer substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoning will be more readily apparent upon reading the followingdescription in conjunction with the drawings in which like elements indifferent figures have the same reference numeral and wherein:

FIG. 1 schematically depicts a cross section of a typical prior arthybrid package;

FIG. 2 is a partially exploded perspective view of a package constructedin accordance with the principles of this invention;

FIG. 3 schematically depicts a partially exploded cross sectional viewthrough the package of FIG. 2, taken along the line 3--3;

FIGS. 4A-4E illustrate alternate configurations of sealing arrangements;

FIGS. 5A-5G schematically depict the steps for an exemplary multi-layerconductor/polymer substrate fabrication; and

FIGS. 6A-6H schematically depict the steps for an alternate multi-layerconductor/polymer substrate fabrication.

DETAILED DESCRIPTION

FIG. 1 schematically illustrates a cross-section of a typical prior arthybrid package, designated generally by the reference numeral 10. Thepackage 10 includes a case 12, typically formed of Kovar alloy, to whichis metallurgically joined a lid 14 to form a hermetic enclosure. Aceramic substrate 16 is bonded to the case 12 and has mounted thereon aplurality of semiconductor chips 18 which are wire bonded to signaltraces (not shown) on the surface of the substrate 16 in a conventionalmanner. To provide input/output connections to and from the chips 18,appropriate ones of the signal traces are wire bonded to leads 20. Theleads 20 pass through the case 12 via glass-to-metal seals 22 in orderto maintain the hermeticity of the package 10. The leads 20 are thenprepared for subsequent solder attachment to a printed wiring board.

Known disadvantages of the aforedescribed type of package include alimit to the allowable number of input/output connections leaving thehermetic enclosure for a given package size. Further, theinterconnection seals are a significant source of hermetic seal failure.Another problem is that reworking and repairing the hybrid circuit isdifficult and there is a limit to the testing and fault isolation whichca be performed after sealing of the package. Still further, thesubstrate typically possesses poor electrical characteristics,especially regarding high speed transmission and shielding.

To overcome the aforementioned disadvantages, the very large hybridmodule package depicted in FIGS. 2 and 3 was developed. This package,designated generally by the reference numeral 24, utilizes a dualsubstrate approach. As will be described in full detail hereinafter, thefirst substrate is used for mounting the electronic components,attaching the lid, and providing part of the hermetic barrier. Thesecond substrate is outside the hermetic closure and is used forproviding interconnections between the electronic components.

As shown in the drawings, the package 24 includes a first substrate 26and a second substrate 28. In accordance with this invention, the firstsubstrate 26 has hermetic properties and is generally planar withparallel first and second surfaces 30 and 32, respectively. The firstsurface 30 has a plurality of electronic components 34 mounted thereon,the electronic components 34 being grouped within discrete regions ofthe first surface 30. Each of the regions is surrounded by a seal ring36 which is hermetically mounted on the surface 30. Hermetically joinedto each of the seal rings 36 is a hermetic lid member 38. Accordingly,all of the electronic components 34 mounted within a discrete region arecontained within a hermetic enclosure, formed by the first substrate 26,a respective seal ring 36, and a respective lid member 38.

As mentioned above, the first substrate 26 provides a hermetic barrier.Preferably, the substrate 26 is formed of a ceramic. More particularly,the substrate 26 is actually several co-fired layers of ceramic withmetallization. Preferred ceramics are aluminum oxide and aluminumnitride. On the surface 30 of the substrate 26, there are various areasof metallization. These include input/output connector lands 40,component interconnect pads 42 to which the leads of the components 34are electrically connected, as well as the seal rings 36. A majority ofinterconnections between these areas of metallization are effectedthrough the second substrate 28, although the first substrate 26 maycontain internal power and/or ground planes and/or some functionalinterconnect. Accordingly, the first substrate 26 has a first pluralityof metallized vias 44 extending therethrough from the first surface 30to the second surface 32. These vias 44 are in electrical contact withthe areas of metallization on the first surface 30. The vias 44illustratively are formed during the co-firing of the ceramic substrate26. Alternatively, the vias could be formed by laser drilling andsubsequent metallization of pre-fired ceramic.

The second substrate 28 is generally planar with parallel first andsecond surfaces 46 and 48, respectively. The first surface 46 of thesecond substrate 28 is in intimate contact with the second surface 32 ofthe first substrate 26. A second plurality of metallized vias 50 extendfrom the first surface 46 to the second surface 48 of the secondsubstrate 28 and are in effect, extensions of the first plurality ofmetallized vias 44. To effect a desired connection pattern between theelectronic components 34, the second substrate 28 is formed withconductive signal traces between appropriate ones of the secondplurality of metallized vias 50. Thus, to effect connections to theinput/output connector lands 40, input/output signal traces 52 areprovided. To make connections between electronic components within adiscrete region, intra-region signal traces 54 of minimized interconnectlength are provided. Finally, to make connections between electroniccomponents in different regions, inter-region signal traces 56 areprovided.

FIGS. 4A-4E illustrate alternative configurations for the lid 38 joinedto the metallized seal ring 36 on the surface 30. FIG. 4A shows a deepdrawn lid 38 without a flange that is soldered to the seal ring 46. FIG.4B shows a deep drawn lid 38 with a flange that is soldered to the sealring 36. In FIGS. 4C, 4D and 4E, intermediate seal ring members 58, 60and 62, respectively, are brazed to the seal ring 36 and are then joinedto the lid 38 by solder or a weld.

FIGS. 5A-5G illustrate the steps for forming the second substrate 28using a plated post via method. As shown in FIG. 5A, initially the firstsubstrate 26 is obtained and placed with the component mounting surface30 on the bottom. Next, as shown in FIG. 5B, a conductive adhesion layeris sputtered to the surface 32. As shown in FIG. 5C, photoresist isapplied and patterned, and the via pads are plated. As shown in FIG. 5D,the resist is removed, photoresist is applied and patterned, and the viaposts are plated. As shown in FIG. 5E, the resist is removed, theadhesion layer is etched, liquid polymer is spin coated on the surface,and the polymer is cured. As shown in FIG. 5F, the polymer surface is"planarized" by a lapping process to expose the via posts. As shown inFIG. 5G, the aforedescribed steps are repeated to build additionallayers.

FIGS. 6A-6H illustrate the steps in obtaining an etched via substrate28. As shown in FIG. 6A, initially the first substrate 26 is placed withits component mounting surface 30 on the bottom. As shown in FIG. 6B, aconductive adhesion layer is sputtered onto the surface 32. As shown inFIG. 6C, photoresist is applied and patterned, and the via pads areplated. As shown in FIG. 6D, the resist is removed, the adhesion layeris etched, liquid polymer is spin coated on the surface, and the polymeris cured. As shown in FIG. 6E, the vias are either reactive ion etched(RIE) or laser drilled. As shown in FIG. 6F, an adhesion layer is thensputtered onto the surface. As shown in FIG. 6G, photoresist is appliedand patterned, and a conductor pattern is plated. As shown in FIG. 6H,the aforedescribed steps are repeated to build additional layers for thesubstrate 28.

In accordance with this invention, the second plurality of metallizedvias 50 are exposed at the second surface 48 of the second substrate 28.Accordingly, after the components 34 are mounted on the surface 30, themodule may be electrically tested from the surface 48. Then, thehermetic lid members 38 are sealed the module is re-tested from thesecond surface 48. If a component is found to be defective, theappropriate lid 38 can be removed, the component replaced, and the lidresealed. Furthermore, if it is desired to change the interconnectionpattern, the second substrate 28 is accessible so that the signal tracescan be cut and jumpers installed, all without requiring removal of thelid members 38. After all testing has been performed and any desiredchanges to the interconnection pattern have been effected, the secondsurface 48 may have an insulating overcoat applied.

Accordingly, there has been disclosed an improved hybrid moduleelectronics package. While illustrative embodiments of the presentinvention have been disclosed herein, it will be apparent to those ofordinary skill in the art that various modifications and adaptations tothose embodiments are possible and it is only intended that the presentinvention be limited by the scope of the appended claims.

We claim:
 1. A hybrid module of electronic circuitry comprising:a firstsubstrate having hermetic properties, said first substrate havinggenerally planar parallel first and second surfaces; a plurality ofelectronic components mounted on the first surface of said firstsubstrate, said plurality of components being grouped within discreteregions of said first surface; enclosure means for providing a pluralityof hermetic enclosures on said first surface, each of said hermeticenclosures surrounding the components within a respective discreteregion; a second substrate having organic properties, said secondsubstrate having generally planar parallel first and second surfaces,the first surface of said second substrate being in intimate contactwith and electrically interconnected to the second surface of said firstsubstrate; .[.and interconnection means for providing connectionsbetween said plurality of electronic components through said secondsubstrate so that testing of said electronic components can be effectedwithout invasion said hermetic enclosures.]. .Iadd.a plurality ofcomponent interconnect pads on said first substrate first surface; meansfor electrically connecting the leads of said electronic components torespective ones of said component interconnect pads; a first pluralityof metallized vias through said first substrate in contact withrespective ones of said component interconnect pads, said firstplurality of vias extending from said first surface to said secondsurface of said first substrate; a second plurality of metallized viasthrough said second substrate, said second plurality of vias being incontact with respective ones of said first plurality of vias, extendingfrom said first surface to said second surface of said second substrate,and exposed to said second substrate second surface; and a plurality ofconductive signal traces within said second substrate interconnectingsaid second plurality of vias so as to provide a desired pattern ofconnections between the leads of said electronic components; wherebytesting of said electronic components can be effected from said secondsubstrate second surface without invasion of said hermeticenclosures.Iaddend..
 2. A module according to claim 1, wherein saidenclosure means includes:a plurality of hermetic seal rings hermeticallymounted on said first substrate first surface, each of said seal ringssurrounding a respective discrete region; and a plurality of hermeticlid members each hermetically joined to a respective one of said sealrings so as to provide a plurality of enclosed spaces each containingthe electronic components within a respective discrete region.
 3. Amodule according to claim 1 wherein said first substrate is formed of aceramic.
 4. A module according to claim 3 wherein said ceramic is aco-fired ceramic.
 5. A module according to claim 4 wherein said ceramicis selected from the group consisting of aluminum oxide and aluminumnitride.
 6. A module according to claim 1 wherein said organic materialis a polymer. .[.
 7. A module according to claim 1 wherein saidinterconnection means includes:a plurality of conductive pads on saidfirst substrate first surface; means for electrically connecting theleads of said electronic components to respective ones of said pads; afirst plurality of metallized vias through said first substrate incontact with respective ones of said pads, said first plurality of viasextending from said first surface to said second surface of said firstsubstrate; a second plurality of metallized vias through said secondsubstrate, said second plurality of vias being in contact withrespective ones of said first plurality of vias and extending from saidfirst surface to said second surface of said second substrate; and aplurality of conductive signal traces through said second substrateinterconnecting said second plurality of vias so as to provide a desiredpattern of connections between the leads of said electroniccomponents..].
 8. A module according to claim .[.7.]. .Iadd.1.Iaddend.wherein said second substrate, said plurality of conductivesignal traces and said second plurality of metallized vias are togetherformed as a multi-layer conductor/polymer substrate.